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ISL6615
PVCC
BOOT
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
(EQ. 2)
D
P Qg_Q1 = --------------------------------------- ? F SW ? N Q1
Q G1 ? PVCC 2
V GS1
R HI1
G
C GD
C DS
P Qg_Q2 = --------------------------------------- ? F SW ? N Q2
Q G2 ? PVCC 2
V GS2
R LO1
R G1
R GI1
C GS
S
Q1
PHASE
I DR = ? ----------------------------------------------------- + ----------------------------------------------------- ? ? F SW + I Q
? Q G1 ? PVCC ? N Q1 Q G2 ? PVCC ? N Q2 ?
? V GS1 V GS2 ?
(EQ. 3)
where the gate charge (Q G1 and Q G2 ) is defined at a
particular gate to source voltage (V GS1 and V GS2 ) in the
corresponding MOSFET datasheet; I Q is the driver ’s total
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
quiescent current with no load at both drive outputs; N Q1
and N Q2 are the number of upper and lower MOSFETs,
respectively; PVCC is the drive voltage for both upper and
lower FETs. The I Q *VCC product is the quiescent power of
the driver without capacitive load and is typically 200mW at
300kHz and VCC = PVCC = 12V.
R HI2
R LO2
G
R G2
C GD
R GI2
C GS
C DS
Q2
S
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R G1 and R G2 ) and the internal gate resistors
(R GI1 and R GI2 ) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated, as shown in Equation 4.
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
Layout Considerations
The parasitic inductances of the PCB and of the power
devices’ packaging (both upper and lower MOSFETs) can
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P DR_LOW = ? ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
P DR = P DR_UP + P DR_LOW + I Q ? VCC
? R HI1 R LO1 ? P Qg_Q1
? R HI2 R LO2 ? P Qg_Q2
-------------------------------------- + ----------------------------------------
2
2
(EQ. 4)
cause serious ringing, exceeding the device’s absolute
maximum ratings. A good layout helps reduce the ringing on
the switching node (PHASE) and significantly lowers the
stress applied to the output drives. The following advice is
meant to lead to an optimized layout and performance:
? Keep decoupling loops (VCC-GND, PVCC-GND and
BOOT-PHASE) short and wide (at least 25 mils). Avoid
using vias on decoupling components other than their
R EXT1 = R G1 + -------------
R EXT2 = R G2 + -------------
R GI1
N Q1
8
R GI2
N Q2
ground terminals, which should be on a copper plane with
at least two vias.
? Minimize trace inductance, especially on low-impedance
lines. All power traces (UGATE, PHASE, LGATE, GND,
PVCC, VCC, GND) should be short and wide (at least
25 mils). Try to place power traces on a single layer,
otherwise, two vias on interconnection are preferred
where possible. For no connection (NC) pins on the QFN
part, connect it to the adjacent net (LGATE2/PHASE2) can
reduce trace inductance.
FN6481.0
April 24, 2008
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